1. Field of Invention
The present invention generally relates to integrated circuit (“IC”) and electronics design processes and electronic design automation tools. More specifically, the present invention relates to automated IC design data and, more specifically, to routing congestion removal during pin optimization, particularly for custom IC design.
2. Description of Related Art
A typical custom design flow 100 is shown in FIG. 1. After design entry 101, layout generation 103 and initial design 105 follow floorplanning. As shown in FIG. 1, the floorplanning stage 107 includes block placement 109 and pin optimization 111. During pin optimization 111, pins of blocks and top level design blocks are placed based on connectivity to minimize the overall wire length. Even though the wire length is minimized in this process, many times the pin optimization results in hot spots (highly congested areas) in order to minimize wire-length. Global routing 113 provides the congestion data in the design. If there are high congestion areas in the design 115, then the designer will either manually re-position the pins 117 or, alternately, restart pin optimization on selected pins with a new set of constraints until the level of congestion is acceptable and continuing on 119.
There does not currently exist any solution in the custom IC design domain to consider congestion during pin optimization. Hence it is a repetitive task to run the global router and re-position pins manually to minimize congestion in the design in order to get the desired results.